Fundamental to the operation of virtually all digital microprocessors is the function of digital (i.e., binary) addition. Addition is used not only to provide numerical sums that a user is conscious of, but also in the implementation of numerous logic functions. In a typical microprocessor, many adders are used for these functions. When two digital words are added, the carry bit that results from the addition of the lesser significant bits must be considered. This can easily be done by rippling a carry signal as the addition is performed. A problem with this, particularly for relatively large words (e.g., 32 bits) is that substantial time is required to ripple the carry signal through the entire addition chain. And since the adders are often performing logic functions in critical time paths, the time needed to ripple the carry signal can slow up the microprocessor. This problem is dealt with in the prior art with carry look ahead circuits, skip-carry circuits and with different partitioning of group circuitry. These circuits are discussed in U.S. Pat. No. 4,737,926.
Thus, what is needed is an improved skip-carry adder that has fewer delays along critical paths in the adder and provides substantial improvement in terms of speed of operation when compared to prior art adders.